The present invention relates to digital infinite impulse response (IIR) equalizer filters.
Digital Filters
A filter, simply put, is a system which modifies certain frequencies relative to others. A digital filter exists when the sets of inputs and outputs of a given filter are digital, i.e. they can assume only a finite number of possible amplitude values. Implementation of a digital filter requires that the function that operates on the set of inputs be reduced to a computational algorithm. A structure, or network, can then be implemented to produce the function.
Digital filters are generally defined by difference equations. A difference equation for a given filter will reveal the expected characteristics of the filter, such as the frequency poles and zeros and the order of the system. IIR Filters with a single frequency pole are known as first-order filters. IIR Filters with two frequency poles are known as second-order filters. First and second order filters are the most general and utilitarian designs of digital filters. They can be combined in parallel or cascade combinations to create filters of higher orders.
Most digital filters can be implemented with a combination of addition, multiplication, and delay elements or operations. General-purpose computers, including personal computers (or "PCs") or hardware such as a digital signal processor (or "DSP") may be used to implement a digital filter with these elements. In either case, the implementation of the filter serves as the specification, that is, the manner in which it is to perform. Computers and "host DSPs" utilize this specification as an algorithm specifying use of the control unit, arithmetic unit, storage registers, and multipliers (in a host DSP) to produce the desired set of outputs. Some dedicated-DSPs (or "DSP-ASICs") use the structure as a hardware configuration specification.
DSPs
DSPs, as implemented in very-large-scale integration (or "VLSI") circuits, are ideally suited to uses which require resources beyond the abilities of general-purpose computers. Such uses include processing of large amounts of data or where manipulation of data requires a high sampling rate or higher resolution per sample. A "host DSP" is a general-purpose DSP designed to accommodate a wide range of processing applications. As such, it offers a speed increase over general-purpose computers. A DSP-ASIC is designed with a specific application in mind. Therefore, it offers a speed advantage at least comparable to a host DSP as well as size and cost advantages due to its application-specific implementation.
The design characteristics of digital filters make them well suited to implementation in a DSP. The small number of elements used to describe a digital filter, combined with their highly parallel algorithmic structure, allow digital filters to readily be put into the context of a DSP.
DSPs offer not only higher speeds and resolutions than are available with general-purpose computer implementations of digital filters, but also lower cost and less space demand. The main advantage of DSP implementation of a digital filter is that the filter elements (addition, multiplication, and delay), as opposed to a general-purpose computer, do not have to be performed in sequence. That is, the DSP implementation offers opportunities for the elements to be performed in parallel. This results in increased throughput as compared to a general-purpose computer implementing the same filter.
Frequency Shelf Filters
FIGS. 5A and 5B graphically depict the functions of frequency shelf filters. Frequency shelf filters have a frequency response of unity at either 0 or fs/2, where fs is the frequency sample rate. A low-frequency shelf filter has a frequency response of unity at fs/2 and increases (or decreases) monotonically toward 0. A high-frequency shelf filter has a frequency response of unity at 0 and increases (or decreases) monotonically toward fs/2.
Frequency shelf filters are used in digital tone processing of audio signals. FIG. 5A represents the frequency response of a low-frequency shelf filter. FIG. 5B represents the frequency response of a high-frequency shelf filter. Generally, the boost and cut responses represented in each figure are chosen to be symmetric. FIGS. 5A and 5B reflect that both low and high frequency shelf filters are tied to a frequency response of unity at one end, 0 or fs/2. Therefore, frequency shelf filters can be implemented as digital first-order or higher order IIR filters.
A digital first-order filter can be represented by the transfer function H(z): ##EQU1##
where b.sub.o,b.sub.1, and a.sub.1 are filter coefficients and the term z.sup.-1 relates to a one time-unit delay. The coefficients of a particular filter are calculated using one of several theoretical design procedures: Butterworth, Chebyshev, elliptic, etc. The design procedure produces values for the needed coefficients based on parameters for the filter such as frequency response.
In time domain, the above representation of H(z) gives: EQU y(n)=b.sub.0 x(n)+b.sub.1 x(n-1)-a.sub.1 y(n-1).
Implementation of the above difference equation as a digital filter requires 3 multiply operations and three corresponding coefficient memory elements, one for each filter coefficient, b.sub.0, b.sub.1, and a.sub.1.
Equalizer Filters
FIG. 3 graphically depicts the functions of an equalizer. An equalizer is a digital second-order IIR filter structure that allows boosting (gain larger than unity as in curve 304) or cutting (gain smaller than unity as in curve 306) of input signal frequencies centered around some design frequency f.sub.0 .di-elect cons. (0, fs/2). The gain is unity at the endpoints 0 and fs/2. Thus, the equalizer frequency response function H(e.sup.jw) must have H(e.sup.j0)=H(e.sup.ifs/2)=1.
Equalizers such as this are routinely used in audio tone control and speaker and room equalization in products such as consumer/PC audio, video, DVD and home theaters.
The current and future applications of digital equalizers necessitate DSP capacity enhancement. That is, it would be desirable to allow more equalizer processing than is currently available without incurring extra costs or increased space demands.
FIGS. 2A and 2B, described in detail below, schematically show the direct form I (DFI-type) and direct form II (DFII-type) implementation architectures for a second order IIR digital filter. A DFI-type implementation is the network realization corresponding to a difference equation which describes a particular filter. A DFII-type, or canonical, implementation is a DFI-type implementation which uses the minimum number of delay elements required for realization of the difference equation. Note that in either implementation, a second order IIR digital filter includes 5 multiply elements or operations.
Any reduction in the number of multipliers that can be achieved in the implementation of a digital filter, even at the expense of a greater number of addition elements, is significantly advantageous. Multiply operations tend to keep the DSP very busy due to the complexity of the mathematical operation. A reduction in multipliers decreases the number of clock cycles required for the filter to produce an output. Further, as multipliers are more complex than addition elements, the monetary cost of the implementation is reduced.
Finally, the physical size of the DSP on which the digital filter is implemented can be reduced due to fewer components being needed to produce the same result. As a corollary, instead of reducing chip size, a DSP could implement more digital filters with the same number of multipliers with only slight variation to the architecture, including an increase in the number of addition elements.
Reduced Multiplier Digital Filters
The present application discloses that digital equalizer filters can be implemented with fewer multipliers. The present disclosure uses at least one fewer multiplier for first and second order filters than current solutions. The present application discloses a 2-multiplier approach to first-order digital frequency shelf filters. Further, the present application discloses a 3 multiplier approach to second-order digital e-qualization filters.
In both instances, this new filter structure uses at least one fewer multiplier than present digital equalizer structures. This multiplier reduction enhances the capacity of the current audio equalizer DSP by 30 percent. The disclosed reduction in the number of multipliers required to implement some digital IIR equalization filter provides several advantages. One advantage is that the processing capacity of the audio equalizer DSP is enhanced by reducing the computational requirements imposed by first and second order digital IIR filters. That is, the number of multiply operations for first-order structures is reduced by 33 percent and the number of multiply operations for second-order structures is reduced by 25 percent. For current and future DSPs, this multiplier-efficient structure would, as an example, enhance an 11-filter capacity DSP to at least a 14-filter capacity. This allows having the ability to provide enhanced and differentiated processing features for the same cost. For instance, instead of a 5-band stereo equalizer, the DSP can provide a 7-band stereo equalizer for substantially the same cost. Another practical advantage is that the present disclosure requires approximately 20 percent less computation in a microcode implementation of a DSP or one less multiplier in a dedicated hardware DSP and requires one fewer coefficient storage word in either case. This results in faster computational output and reduced cost.